Technology Labs
VL-ZYNQ-ULTRA - Zynq UltraScale+ MPSoC with Carrier Development Board
About Product
The Zynq UltraScale+ MPSoC (Multi-Processor System-on-Chip) is a high-performance heterogeneous multiprocessing architecture developed by Xilinx. It integrates a feature-rich Processing System (PS) and an advanced Programmable Logic (PL) FPGA fabric onto a single 16nm FinFET die, delivering up to 5X greater system performance-per-watt compared to previous generations
1) Powered by ARM® Quad-Core Cortex™A53 MP Core
2) Based on Xilinx’s high-end Zynq MpSoC Series. All-Programmable SoC
3) Support Zynq devices ZU1, ZU2, ZU3 CG / EG series 484 Pin package devices
4) 95 mm x 75 mm board size Compact form factor
5) Available in Production ready with industrial temperature range
6) Linux BSP, tool chain and 24x7 Technical Support
7) Combines Flexibility of SBC with the FPGA configurability
8) Industrial Grade, Rugged platform to optimize overall BOM cost
9) On module required power supplies for efficient power management.
10) Linux board support package along with Root file system enables seamless integration
11) Customized Carrier boards for instant board bring-up and quick prototyping
2) Based on Xilinx’s high-end Zynq MpSoC Series. All-Programmable SoC
3) Support Zynq devices ZU1, ZU2, ZU3 CG / EG series 484 Pin package devices
4) 95 mm x 75 mm board size Compact form factor
5) Available in Production ready with industrial temperature range
6) Linux BSP, tool chain and 24x7 Technical Support
7) Combines Flexibility of SBC with the FPGA configurability
8) Industrial Grade, Rugged platform to optimize overall BOM cost
9) On module required power supplies for efficient power management.
10) Linux board support package along with Root file system enables seamless integration
11) Customized Carrier boards for instant board bring-up and quick prototyping
SYSTEM-ON-MODULE — Zynq MpSoC Series
Processor:
1) EG - Quad-core Arm Cortex-A53 MPCore up to 1.5GHz and Dual-core ARM Cortex-R5 MPCore up to 600MHz
2) Enhanced NEON Extension and Single & double precision FPU
3) CG -Dual-core Arm® Cortex®-A53 MPCore™up to 1.3GHz and Dual-core Arm Cortex-R5F MPCore up to 533MHz
4) 64KB Unified L2 Cache
5) 32KB Instruction and Data L1 cache
6) 256KB On-chip Memory for application core
Memory
1) 4 / 8GB LPDDR4 Support
2) 16Gb/32Gb eMMC
3) 16MB/32MB QSPI support
FPGA
1) Xilinx ZynqMP Advanced low power FPGA fabric
2) Up to 154K Logic Cells (approximately 141K Flops)
3) Upto 360 programmable DSP slices
Power Supply
1) 12V
2) 7W (Max)
Power supply sequencer
1) ATMEGA328P Power supply sequencing & monitoring
Boot Support
1) JATG / QSPI / uSD / eMMC
Ethernet - 4 Nos
1) 2 x 1Gbps VSC8211 Optical Ethernet Modules
2) 4 x 10/100/1000 BASE-T KSZ9031 Ethernet module
USB
1) 1 x USB 2.0 OTG
Display
1) Through LVDS Interface / Display Port
Additional Interfaces
1) CAN 2.0 / UART (Optional on IOs assignments )
2) 170 FPGA IO’s
3) Analog Inputs (Multiplex and Shared)
MicroSD
1) 1 x MicroSD support upto 32GB
Form Factor
1) 90 mm x 70 mm2 x 100 Pin High Speed Connectors
Software Support
1) Linux, BSP
On Board Unique Encryption ID supportDisplay
On Board RTC, Battery Support on Carrier Card
On Board Unique MAC ID support
SiEN - Carrier Card
Key Specs
1) User GPIO Monochrome LEDs
2) On board RS485 interface
3) On Board isolated 2 x DI and 2 x DO
4) On Board RTC, Battery
5) On Board additional GPIO interface
6) On Board Unique MAC ID support
7) On board 4 x RJ45 & 2 x SFP Connector
8) On board JTAG and UART debug interface
9) User Slide Switch and Push Button I/O
Additional Interfaces
1) CAN 2.0 / UART (Optional on IOs assignments )
2) 170 FPGA IO’s
3) Analog Inputs (Multiplex and Shared)
Power Supply
1) 5V
USB
1) 1 x USB 2.0 OTG
Ethernet - 4 Nos
1) 2 x SFP Optical Ethernet Connector
2) 4 x RJ45 Copper Connector
MicroSD
1) 1 x MicroSD support upto 32GB
Display
1) Through LVDS Interface / Display Port
Serial
1) 1 x UART, 1 x I2C, 1X CAN2.0
Form Factor
1) 1600 mm x 125 mm
2) 2 x 100 Pin High Speed Connectors
SOFTWARE
AMD Vivado Design Suite and the AMD Vitis Software Platform are powerful tools made by AMD (formerly Xilinx) for designing systems on FPGAs (Field Programmable Gate Arrays) and adaptive SoCs (System on Chips).
AMD Vivado
Hardware-centric design
Core tasks: Handles design entry (writing Verilog, VHDL, or block diagrams),
Output: Generates the hardware bitstream file,Design Entry: Write hardware code using VHDL or Verilog, or use visual block diagrams via the IP Integrator.
AMD Vitis
Software-centric design: Used for writing the software that runs on the processors (like Arm cores) inside your SoC or managing high-level synthesis (HLS).
Core tasks: Developing bare-metal/standalone drivers, Free RTOS, or embedded Linux applications.
Integration: You import the XSA file exported from Vivado into Vitis to let the software environment know what hardware peripherals and memory maps are available. Testing codes provided for the board involves testing codes, testbenches with verifying pin functionality, and checking the peripheral communication.
Processor:
1) EG - Quad-core Arm Cortex-A53 MPCore up to 1.5GHz and Dual-core ARM Cortex-R5 MPCore up to 600MHz
2) Enhanced NEON Extension and Single & double precision FPU
3) CG -Dual-core Arm® Cortex®-A53 MPCore™up to 1.3GHz and Dual-core Arm Cortex-R5F MPCore up to 533MHz
4) 64KB Unified L2 Cache
5) 32KB Instruction and Data L1 cache
6) 256KB On-chip Memory for application core
Memory
1) 4 / 8GB LPDDR4 Support
2) 16Gb/32Gb eMMC
3) 16MB/32MB QSPI support
FPGA
1) Xilinx ZynqMP Advanced low power FPGA fabric
2) Up to 154K Logic Cells (approximately 141K Flops)
3) Upto 360 programmable DSP slices
Power Supply
1) 12V
2) 7W (Max)
Power supply sequencer
1) ATMEGA328P Power supply sequencing & monitoring
Boot Support
1) JATG / QSPI / uSD / eMMC
Ethernet - 4 Nos
1) 2 x 1Gbps VSC8211 Optical Ethernet Modules
2) 4 x 10/100/1000 BASE-T KSZ9031 Ethernet module
USB
1) 1 x USB 2.0 OTG
Display
1) Through LVDS Interface / Display Port
Additional Interfaces
1) CAN 2.0 / UART (Optional on IOs assignments )
2) 170 FPGA IO’s
3) Analog Inputs (Multiplex and Shared)
MicroSD
1) 1 x MicroSD support upto 32GB
Form Factor
1) 90 mm x 70 mm2 x 100 Pin High Speed Connectors
Software Support
1) Linux, BSP
On Board Unique Encryption ID supportDisplay
On Board RTC, Battery Support on Carrier Card
On Board Unique MAC ID support
SiEN - Carrier Card
Key Specs
1) User GPIO Monochrome LEDs
2) On board RS485 interface
3) On Board isolated 2 x DI and 2 x DO
4) On Board RTC, Battery
5) On Board additional GPIO interface
6) On Board Unique MAC ID support
7) On board 4 x RJ45 & 2 x SFP Connector
8) On board JTAG and UART debug interface
9) User Slide Switch and Push Button I/O
Additional Interfaces
1) CAN 2.0 / UART (Optional on IOs assignments )
2) 170 FPGA IO’s
3) Analog Inputs (Multiplex and Shared)
Power Supply
1) 5V
USB
1) 1 x USB 2.0 OTG
Ethernet - 4 Nos
1) 2 x SFP Optical Ethernet Connector
2) 4 x RJ45 Copper Connector
MicroSD
1) 1 x MicroSD support upto 32GB
Display
1) Through LVDS Interface / Display Port
Serial
1) 1 x UART, 1 x I2C, 1X CAN2.0
Form Factor
1) 1600 mm x 125 mm
2) 2 x 100 Pin High Speed Connectors
SOFTWARE
AMD Vivado Design Suite and the AMD Vitis Software Platform are powerful tools made by AMD (formerly Xilinx) for designing systems on FPGAs (Field Programmable Gate Arrays) and adaptive SoCs (System on Chips).
AMD Vivado
Hardware-centric design
Core tasks: Handles design entry (writing Verilog, VHDL, or block diagrams),
Output: Generates the hardware bitstream file,Design Entry: Write hardware code using VHDL or Verilog, or use visual block diagrams via the IP Integrator.
AMD Vitis
Software-centric design: Used for writing the software that runs on the processors (like Arm cores) inside your SoC or managing high-level synthesis (HLS).
Core tasks: Developing bare-metal/standalone drivers, Free RTOS, or embedded Linux applications.
Integration: You import the XSA file exported from Vivado into Vitis to let the software environment know what hardware peripherals and memory maps are available. Testing codes provided for the board involves testing codes, testbenches with verifying pin functionality, and checking the peripheral communication.
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